Self track scheme for multi frequency band serializer de-serializer I/O circuits

ABSTRACT

A serializer and de-serializer circuit having self tracking circuitry which is particularly well-suited for use in communicating digital data from one integrated circuit (chip) to another for implementing chip-to-chip communications is presented. The circuits are scalable and utilize a multi-frequency modulation mechanism (e.g., QAM) for converting digital data bits into a serial analog stream at multiple frequencies for communication over a chip I/O connection. The track pulse generated on the transmitter side is serialized through the same path as the data, and demodulated through the same path in the de-serializer to provide synchronization with the data, without the need for complicated base band processing.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a 35 U.S.C. §111(a) continuation of PCTinternational application number PCT/US2013/066194 filed on Oct. 22,2013, incorporated herein by reference in its entirety, which claimspriority to, and the benefit of, U.S. provisional patent applicationSer. No. 61/723,284 filed on Nov. 6, 2012, incorporated herein byreference in its entirety. Priority is claimed to each of the foregoingapplications.

The above-referenced PCT international application was published as PCTInternational Publication No. WO 2014/074301 on May 15, 2014, whichpublication is incorporated herein by reference in its entirety.

STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

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INCORPORATION-BY-REFERENCE OF MATERIAL SUBMITTED IN A COMPUTER PROGRAMAPPENDIX

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NOTICE OF MATERIAL SUBJECT TO COPYRIGHT PROTECTION

A portion of the material in this patent document is subject tocopyright protection under the copyright laws of the United States andof other countries. The owner of the copyright rights has no objectionto the facsimile reproduction by anyone of the patent document or thepatent disclosure, as it appears in the United States Patent andTrademark Office publicly available file or records, but otherwisereserves all copyright rights whatsoever. The copyright owner does nothereby waive any of its rights to have this patent document maintainedin secrecy, including without limitation its rights pursuant to 37C.F.R. §1.14.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention pertains generally to chip-to-chip communications, andmore particularly to a self tracking serializer de-serializer.

2. Description of Related Art

Conventional serializer de-serializer I/O is based on multiplexing anddemultiplexing digital communications. Using such conventional schemesto increase communications bandwidth requires increasing clock rate.

Attempting to use multi-frequency bands in a traditional scheme formodulation and demodulation to overcome the above problems brings upadditional issues. Current multi-frequency serializers andde-serializers for use with chip-to-chip I/O include modulation anddemodulation that are complicated and dependent on external factors,such as silicon process, connection conditions, power supply quality,and the like. In these conventional systems, a complicated scheme, suchas error correction or base band processing is required to achievereliable modulation and demodulation with low bit error rate. When thelatency of modulation and demodulation becomes critical in the I/Oconnection, the traditional base band processing, used to ensure lowbit-error-rate (BER), in modulation and demodulation becomesimpractical.

The use of base band processing techniques can in some cases provide forreliable data transmission and reception, yet it comes with a high costpenalty regarding circuit complexity and unnecessarily long delays fordata processing. Although the typical multi-frequency approach may besuitable for high throughput operations, it is not well suited whenshort latencies are required to perform mission critical operations.

Accordingly, a need exists for chip-to-chip multi-frequencycommunication circuits that have short latencies and are readilyimplemented. The present invention fulfills these needs, and overcomesshortcomings of previous multi-frequency chip-to-chip communicationtopologies.

BRIEF SUMMARY OF THE INVENTION

A chip-to-chip serializer and de-serializer are described which utilizea self tracking method based on track pulse generation on thetransmitter (TX) and track pulse restoration on the receiver (RX). Thedata to be transmitted is synchronized with the generated track pulse onTX, with the transmitted data and track pulse being modulated at thesame time in the TX. All signals communicated chip-to-chip utilizing thepresent invention are processed under the same conditions, includingsilicon process variation, power noise, critical path delay, and soforth, thus eliminating/reducing the impact of these variables onoperation of the serializer de-serializer.

Utilizing the inventive self-tracking serializer de-serializer, one canreach the performance limitation for any given technology by not onlyincreasing the data throughput, but in response to also reducing datatransfer latency.

The signals are serialized, modulated and transmitted through a shortI/O connection from transmitter (TX) to receiver (RX). The RX alsodemodulates all signals under the same conditions and characteristics ofthe receiver. The track pulse is restored in the RX after demodulation.Because the data and track pulse are synchronized in the TX, the signalsshould likewise be synchronized in the RX when all signals are processedwith identical demodulation. Once the track pulse is restored, the selftrack scheme can sample the restored data at the correct timing. Thesample timing tracks the external factors even under different operatingconditions, use of different integrated circuit chips or differentprocess technology. The next level of synchronization with the systembus after the signal is sampled in the analog-to-digital converter (ADC)which can also be processed based on the timing of restored track pulse.

The restored track pulse can experience significant jitter in practice.By further use of over-sampling techniques to build a restored trackpulse, the implementation provides an improved large jitter tolerance.

The inventive self tracking serializer de-serializer providessignificant improvements to the yield of chip-to-chip I/O circuits. Theinventive system can be ported to fabricate devices compatible withfuture silicon process advancements, such as from 28 nm nodes to 14 or20 nm nodes with minor effort.

Further aspects of the invention will be brought out in the followingportions of the specification, wherein the detailed description is forthe purpose of fully disclosing preferred embodiments of the inventionwithout placing limitations thereon.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING(S)

The invention will be more fully understood by reference to thefollowing drawings which are for illustrative purposes only:

FIG. 1A and FIG. 1B is a block diagram of a self-trackingmulti-frequency band serializer and de-serializer according to anembodiment of the present invention.

FIG. 2 is a timing diagram of track pulse generation and restorationwithin a self-tracking multi-frequency band serializer and de-serializeraccording to an embodiment of the present invention.

FIG. 3 is a flow diagram of a self tracking serializer de-serializermethod according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

A self tracking serializer de-serializer is described in which a trackpulse is generated which travels along with the digital data throughserialization and modulation at the transmitter (i.e., first chip) andthe demodulation and de-serialization at the receiver (i.e., secondchip). This self tracking ability allows one to build a circuit withminimum timing overhead without complicated base band processing, whileperformance and device yield are achieved with low circuit overhead.Integrated circuits can be fabricated using this self track mechanism inany desired device technology or process, including 28 nm or use ofadvanced silicon process technologies.

FIG. 1A and FIG. 1B illustrate an example embodiment 10 for a selftracking multi-frequency band serializer and de-serializer, shown forcommunicating between a transmitter (TX) in a first chip 12 seen in FIG.1A over an I/O channel 14, to a receiver (RX) in a second chip 16 seenin FIG. 1B.

Digital data 18 (DQ_TX) and byte mask 19 (DM_TX) is seen received in theTX in FIG. 1A. The byte mask is utilized when the data word to becommunicated is sent in multiple sections (e.g., 16 bits over the 8 bitpath shown in FIG. 1A, FIG. 1B). Although the example embodiment oftendescribes a structure allowing sending of 8 bits of digital data (e.g.,[7:0]), it will be appreciated that the present invention can beconfigured with any desired number of bits (e.g., 16 bits, 32 bits, andso forth). However, this requires adding more data buffers, converters(DAC, ADC), and modulators and demodulators operating at morefrequencies or with higher order encoding.

The transmitter controller asserts a synchronization signal 20 (DQS_TX)flag to trigger tracking and serialization. In any embodiment of theinvention, the DQS_TX pulse traverses the whole propagation path towhich the data is subject. A track pulse generator 24 receivessynchronization signal 20 (DQS_TX) and a clock signal 22. The trackpulse generator is configured to generate a synchronized pulse as theflag for data synchronization. It is shown in the figure that DQS_TX isalso applied to a buffer for data mask (DM_TX) 19 and as a first inputof the data buffers 26 a, 26 b, 26 c, on through to 26 m and 26 n, whichalso receive bits within data DQ_TX 18 so that data synchronizes withthe track pulse.

The track pulse and digital data word are serialized and modulated fortransmission to the receiver. Bits of data DQ_TX 18 along with a trackpulse from track pulse generator 24 at modulators 28 a, 28 b, through 28n. Each of these modulators is configured for converting the digitaldata to analog data which is encoded over multiple frequency channels,such as using multiple modulators which are each configured foroperation at a different frequency (e.g., different carrierfrequencies). It should be appreciated that one of these modulationfrequencies can be zero, that is DC. Using DC as one modulationfrequency can reduce the number of frequency generation circuits needed,including phase-locking circuits (e.g., PLL) which are needed. As thesesignals are well known with analog modulation and demodulation thecircuits for generating them are not shown within controllers 62 and 74in FIG. 1A and FIG. 1B, respectively. In one example, each modulatorutilizes quadrature amplitude modulation (QAM) (e.g., QAM16) and hasmixers which encode both an I channel and a Q channel of informationinto a given modulation frequency.

It will be appreciated that QAM, as described in this embodiment, is ananalog modulation mechanism, which differs from digital multiplexingused in a digital serialization scheme. In analog QAM, two analogmessage signals are communicated on each frequency channel by changing(modulating) two carrier waves. The two carrier waves (typicallysinusoids), are out of phase with each other by 90° and are thus calledquadrature carriers. Output over a frequency channel is the sum of themodulated waves of phase modulation (PM) and amplitude modulation (AM).For the sake of simplicity of description, the internal circuitry foranalog QAM is not described. It will be noted that a large number of QAMcircuits are available and the technology is well known to one ofordinary skill in the art. It should be appreciated that a variety offorms of QAM are available and can be utilized with the presentinvention, some of the more common forms that can be selected for useinclude: QAM8, QAM16, QAM32, QAM64, QAM128, and QAM256. It will beappreciated that QAM distributes information in the I-Q plane evenly,and the higher orders of QAM involve information spaced more closely inthe constellation. Thus, higher order QAM allows transmitting more bitsper symbol, but if the energy of the constellation is to remain thesame, the points on the constellation are closer together and thetransmission becomes more susceptible to noise. It should also beappreciated that other forms of modulation (demodulation) can beutilized in the present invention without departing from the teachingsherein. Examples of other forms of multi-frequency modulation which canbe utilized include pulse-width modulation (PWM), frequency-shift keying(FSK), frequency-hopping, spread spectrum, and so forth.

During serialization and modulation in FIG. 1A, digital data isconverted by digital-to-analog converter (DAC) 30 a, 30 b, resulting inanalog outputs received at mixers 32 a, 32 b, through 32 m, 32 n alongwith 90 degree out-of-phase modulation carriers f_(i) and f_(q),respectively. In the example figures, each of the DACs is showncomprising a 2 bit DAC. It should be appreciated, however, thatembodiments can be readily implemented using DACs with a differentnumber of bits, such as 4 or more bits. Each of the modulators 28 a, 28b through 28 n operate at a different frequency, with the output of eachbeing summed at the I/O channel 14 and thus travel through the same I/Oconnection for receipt at second chip 16. This configuration assures aclose tracking of the data path through the same modulation process asthe tracking signal, regardless of the various channel conditions of I/Ochannel 14.

In the receiver (RX) 16 seen in FIG. 1B, all signals are demodulatedthrough the same path, exemplified with demodulators 34 a, 34 b through34 n, each operating at a different frequency within the multiplefrequencies (e.g., which can include zero frequency (DC)). Using QAMdemodulators, each demodulator receives the incoming analog signal attwo mixers (e.g., 36 a and 36 b, 36 c and 36 d, on through to 36 m and36 n) which also receives 90 degree out-of-phase modulation carriersf_(i) and f_(q), respectively. Demodulated output from each of themixers is received by analog-to-digital converters (ADC) 38 a, 38 bthrough 38 m, 38 n. The output from the ADC is only collected insynchronous with the track pulse. By continuously sampling the ADC ofthe track pulse at the TX, this signal can be restored in the RX.

One of the ADCs is seen outputting digital data to a track pulse restorecircuit 40, which operates in combination with output data buffers 42 a,42 b, 42 c, through 42 m and 42 n. A first output 44, comprises therestored track pulse itself used to synchronize the output from the ADCsto the data buffers. Track pulse restore circuit 40 receives a clock 46(CLK_SYS), and outputs a synchronization signal (pulse) 48 forcontrolling the latching of data from the ADCs at each of the databuffers whose output is de-serialized digital data (DQ_RX) 52. Once datafrom the ADCs is latched to the data buffer, the track pulse restorationcircuit sets a flag DQS_RX 50, signaling that the receiver controllercan now read the DQ_RX data word. A byte mask (DM_RX) 51 is alsogenerated for masking purposes when handling multiple bytes.

It will be seen that the track pulse and all data follow through thesame path and time, thus allowing the track pulse restoration circuit togenerate signals for controlling ADC output and latching of the datainto the buffers with proper timing.

The above serializer and de-serializer are particularly well-suited foroperation on a first chip and a second chip between which communicationis to be established. It will be appreciated that a second I/O channelcan be utilized for establishing a communication path in the oppositedirection between the first and second chips. This first and secondchips seen in FIG. 1A and FIG. 1B are each configured with a controller62, 74, respectively, for controlling the transmit and receive sideoperations and generating the signals for operating the serializer andde-serializer. By way of example, and not limitation, the TX controlleris shown having at least one processor circuit 64, comprising CPU 68with memory 70, and utilizing a clock circuit 66. In a similar manner RXcontroller 74 is shown having at least one processor circuit 76,comprising CPU 78 with memory 80, and utilizing a clock circuit 82. Itwill be appreciated, however, that controller circuits can beimplemented with various combinations of discrete and programmable logiccircuits and processors, without departing from the teachings of thepresent invention.

FIG. 2 illustrates an embodiment 90 of signal timing according to theinvention as shown in FIG. 1 for serializing D_TX (e.g., D_TX [7:0]),for transmission from the first chip and upon receipt at the second chipperforming deserialization back into D_RX (e.g., D_RX [7:0]). The upperportion of the figure shows signals on the transmitter (TX) while thelower section shows signals on the receiver (RX). A clock signal(CLK_SYS) is utilized for timing the various actions in the transmittercircuit. The rising edge of CLK_SYS is utilized to strobe DQS_RX andD_RX. A transmitter enable signal (TX_EN) enables data serialization andtransmission. Upon asserting DQS_TX, the TRACK_TX pulses are generatedto which all D_TX data operations are synchronized during modulation.

The lower portion of FIG. 2 depicts TRACK_RX and data D_RX beingrestored. A clock signal (CLK_SYS) is utilized for timing the variousactions in the receiver circuit. A receiver enable signal (RX_EN)enables data deserialization. The TRACK_RX signal is shown experiencingjitter after demodulation. Data output from the ADCs is seen(D_after_ADC) after demodulation. The track pulse restore circuit willperform the restoration of data from the desired eye window and thensynchronizes the data bus with the system clock. The DQS_RX flag signalis seen being generated as data words D_RX and are ready to be read bythe receiver controller.

FIG. 3 illustrates an example embodiment of the tracked method ofserializing and de-serializing according to the invention. Beginningwith step 110, a track pulse start signal is used for starting trackpulse generation and storing 112 a digital data word into buffers formodulation and transmission. The track pulses and digital data word areserialized and modulated 114 into a multi-frequency analog output forreceipt, such as on another chip, by a de-serializer. In thede-serializer, the multi-frequency analog is converted 116 back to adigital data word, and the track pulse is also restored 118.Synchronization signals are generated in response to the restored trackpulse for collecting 120 the digital data word for output. It will benoted that synchronization signals are generated in response to thetrack pulse for: (1) triggering the digital output to the buffers fromthe ADCs, (2) latching digital data onto the buffers; and (3) signalingthat a digital data word is ready.

From the discussion above it will be appreciated that the invention canbe embodied in various ways, including the following:

1. An apparatus for serializing and de-serializing chip-to-chipcommunications, comprising: a serializer configured for serializing andmodulating digital data bits, said serializer having a track pulsegenerator and data buffers whose digital data bit outputs are modulatedby multiple modulators into multiple analog frequency signals configuredfor communication over an I/O channel to an off chip de-serializer; anda de-serializer having multiple demodulators configured for receivingsaid multiple analog frequency signals over the I/O channel anddemodulating these signals for receipt by a track pulse restorationcircuit and data buffers; wherein said track pulse restoration circuitgenerates synchronization signals for triggering output from saiddemodulators to said receiver data buffers, latching data into saidreceiver data buffers, and signaling that digital data bits can be readfrom said receiver data buffers.

2. The apparatus of any of the previous embodiments, wherein saidmodulator and said demodulator operate utilizing quadrature amplitudemodulation (QAM).

3. The apparatus of any of the previous embodiments, wherein saidmodulator and said demodulator operate utilizing quadrature amplitudemodulation (QAM), selected from the group of QAM orders consisting ofQAM8, QAM16, QAM32, QAM64, QAM128 or QAM256.

4. The apparatus of any of the previous embodiments, wherein saidquadrature amplitude modulation (QAM) encodes two analog message signalsinto carrier waves at its carrier frequency.

5. The apparatus of any of the previous embodiments, wherein saiddigital data bits comprises at least 8 bits.

6. An apparatus for serializing and de-serializing chip-to-chipcommunications, comprising: a track pulse generator, configured forgenerating track pulses, within a serializer configured for serializingwords of digital data into multiple analog frequency signals forcommunication to an off chip de-serializer; multiple transmitter databuffers configured for receiving digital data bits; wherein saidmultiple transmitter data buffers load data bits in response to receiptof a synchronization signal which is also received at said track pulsegenerator; multiple modulator circuits, each modulator circuit operatingat a different modulation frequency; said modulator circuits areconfigured for converting said track pulses and outputs from saidmultiple transmitter data buffers into an analog signal modulated intocarriers signals at multiple frequencies for transmission to ade-serializer; and multiple demodulator circuits within a de-serializerconfigured for demodulating and de-serializing data from multiple analogfrequency signals received from a serializer, and outputting digitaldata; wherein each demodulator circuit operates at a differentmodulation frequency; wherein said demodulator circuits are configuredfor converting analog signals modulated into carriers signals atmultiple frequencies into words of digital data; a track pulserestoration circuit, configured for restoring the track pulse from thetransmitter and generating multiple synchronization signals; multiplereceiver data buffers configured for receiving digital data bits fromsaid demodulator circuits; wherein output of digital data from each saiddemodulator is triggered in response to a first synchronization signalfrom said track pulse restoration circuit; wherein said digital datafrom each said demodulator is latched into each of said multiplereceiver data buffers in response to receipt of a second synchronizationsignal from said track pulse restoration circuit; and wherein saiddigital data is read from said data buffers in response to a thirdsynchronization signal from said track pulse restoration circuit.

7. The apparatus of any of the previous embodiments, wherein saidmodulation and demodulation utilizes quadrature amplitude modulation(QAM).

8. The apparatus of any of the previous embodiments, wherein said QAM isselected from the group of QAM orders consisting of QAM8, QAM16, QAM32,QAM64, QAM128 or QAM256.

9. The apparatus of any of the previous embodiments, wherein saidquadrature amplitude modulation (QAM) encodes two analog message signalsinto carrier waves at each output frequency.

10. The apparatus of any of the previous embodiments, wherein saiddigital data bits comprises at least 8 bits.

11. A method for serializing and de-serializing chip-to-chipcommunications, comprising: generating track pulses within a serializerof a first device chip; storing a digital data word for transmissionfrom the first device chip; serializing said track pulses and saiddigital data word and modulating them into multiple frequency analogsignals for communication a de-serializer in a second chip; demodulatingthe multiple frequency analog signals received at a second device chip;performing restoration of the track pulse received from said firstdevice chip; and controlling the collection of said digital data wordinto output buffers in response to synchronization signals timed inrelation to restoration of the track pulse.

12. The method of any of the previous embodiments, wherein said storinga digital data word for transmission is performed with multipletransmitter data buffers which load data bits in response to receipt ofa synchronization signal which is also received at a track pulsegenerator which generates said track pulses.

13. The method of any of the previous embodiments, wherein saidserializing and modulating into multiple frequency analog signals isperformed by multiple modulator circuits, each modulator circuitoperating at a different modulation frequency.

14. The method of any of the previous embodiments, wherein each saidmodulator circuit contains digital-to-analog converters (DACs) coupledto modulating mixers.

15. The method of any of the previous embodiments, wherein saidmodulating and demodulating is performed in response to a quadratureamplitude modulation (QAM) technique.

16. The method of any of the previous embodiments, wherein saidquadrature amplitude modulation (QAM) encodes two analog message signalsinto carrier waves at each output frequency.

17. The method of any of the previous embodiments, wherein saidquadrature amplitude modulation (QAM) is selected from the group of QAMorders consisting of QAM8, QAM16, QAM32, QAM64, QAM128 or QAM256.

18. The method of any of the previous embodiments, wherein saidde-serializing and demodulating from multiple frequency analog signalsis performed by multiple demodulator circuits, each demodulator circuitoperating at a different modulation frequency.

19. The method of any of the previous embodiments, wherein each saiddemodulator circuit contains analog-to-digital converters (ADCs) coupledto demodulating mixers.

20. The method of any of the previous embodiments, wherein saidsynchronization signals timed in relation to restoration of the trackpulse, comprises: a first synchronization signal which triggersdemodulator output of digital data to data buffers; a secondsynchronization signal which latches said digital data onto the databuffers; and a third synchronization signal which indicates that thelatched digital data can be read from the buffers.

Although the description herein contains many details, these should notbe construed as limiting the scope of the disclosure but as merelyproviding illustrations of some of the presently preferred embodiments.Therefore, it will be appreciated that the scope of the disclosure fullyencompasses other embodiments which may become obvious to those skilledin the art.

In the claims, reference to an element in the singular is not intendedto mean “one and only one” unless explicitly so stated, but rather “oneor more.” All structural, chemical, and functional equivalents to theelements of the disclosed embodiments that are known to those ofordinary skill in the art are expressly incorporated herein by referenceand are intended to be encompassed by the present claims. Furthermore,no element, component, or method step in the present disclosure isintended to be dedicated to the public regardless of whether theelement, component, or method step is explicitly recited in the claims.No claim element herein is to be construed as a “means plus function”element unless the element is expressly recited using the phrase “meansfor”. No claim element herein is to be construed as a “step plusfunction” element unless the element is expressly recited using thephrase “step for”.

What is claimed is:
 1. An apparatus for serializing and de-serializingchip-to-chip communications, comprising: a serializer configured forserializing and modulating digital data bits, said serializer having atrack pulse generator and data buffers whose digital data bit outputsare modulated by multiple modulators into multiple analog frequencysignals configured for communication over an I/O channel to an off chipde-serializer; and a de-serializer having multiple demodulatorsconfigured for receiving said multiple analog frequency signals over theI/O channel and demodulating these signals for receipt by a track pulserestoration circuit and data buffers; wherein said track pulserestoration circuit generates synchronization signals for triggeringoutput from said demodulators to said receiver data buffers, latchingdata into said receiver data buffers, and signaling that digital databits can be read from said receiver data buffers.
 2. The apparatusrecited in claim 1, wherein said modulator and said demodulator operateutilizing quadrature amplitude modulation (QAM).
 3. The apparatusrecited in claim 1, wherein said modulator and said demodulator operateutilizing quadrature amplitude modulation (QAM), selected from the groupof QAM orders consisting of QAM8, QAM16, QAM32, QAM64, QAM128 or QAM256.4. The apparatus recited in claim 1: wherein said modulator and saiddemodulator operate utilizing quadrature amplitude modulation (QAM); andwherein said quadrature amplitude modulation (QAM) encodes two analogmessage signals into carrier waves at its carrier frequency.
 5. Theapparatus recited in claim 1, wherein said digital data bits comprise atleast 8 bits.
 6. An apparatus for serializing and de-serializingchip-to-chip communications, comprising: a track pulse generator,configured for generating track pulses, within a serializer configuredfor serializing words of digital data into multiple analog frequencysignals for communication to an off chip de-serializer; multipletransmitter data buffers configured for receiving digital data bits;wherein said multiple transmitter data buffers load data bits inresponse to receipt of a synchronization signal which is also receivedat said track pulse generator; multiple modulator circuits, eachmodulator circuit operating at a different modulation frequency; saidmodulator circuits are configured for converting said track pulses andoutputs from said multiple transmitter data buffers into an analogsignal modulated into carrier signals at multiple frequencies fortransmission to a de-serializer; multiple demodulator circuits within ade-serializer configured for demodulating and de-serializing data frommultiple analog frequency signals received from a serializer, andoutputting digital data; wherein each demodulator circuit operates at adifferent modulation frequency; and wherein said demodulator circuitsare configured for converting analog signals modulated into carriersignals at multiple frequencies into words of digital data; a trackpulse restoration circuit, configured for restoring the track pulse fromthe transmitter and generating multiple synchronization signals; andmultiple receiver data buffers configured for receiving digital databits from said demodulator circuits; wherein output of digital data fromeach said demodulator is triggered in response to a firstsynchronization signal from said track pulse restoration circuit;wherein said digital data from each said demodulator is latched intoeach of said multiple receiver data buffers in response to receipt of asecond synchronization signal from said track pulse restoration circuit;and wherein said digital data is read from said data buffers in responseto a third synchronization signal from said track pulse restorationcircuit.
 7. The apparatus recited in claim 6, wherein said modulationand demodulation utilizes quadrature amplitude modulation (QAM).
 8. Theapparatus recited in claim 7, wherein said QAM is selected from thegroup of QAM orders consisting of QAM8, QAM16, QAM32, QAM64, QAM128 orQAM256.
 9. The apparatus recited in claim 6: wherein said modulator andsaid demodulator operate utilizing quadrature amplitude modulation(QAM); and wherein said quadrature amplitude modulation (QAM) encodestwo analog message signals into carrier waves at each output frequency.10. The apparatus recited in claim 6, wherein said digital data bitscomprises at least 8 bits.
 11. A method for serializing andde-serializing chip-to-chip communications, comprising: generating trackpulses within a serializer of a first device chip; storing a digitaldata word for transmission from the first device chip; serializing saidtrack pulses and said digital data word and modulating them intomultiple frequency analog signals for communication a de-serializer in asecond device chip; demodulating the multiple frequency analog signalsreceived at the second device chip; performing restoration of the trackpulse received from said first device chip; and controlling thecollection of data bits of said digital data word into output buffers inresponse to synchronization signals timed in relation to restoration ofthe track pulse.
 12. The method recited in claim 11, wherein saidstoring a digital data word for transmission is performed with multipletransmitter data buffers which load data bits in response to receipt ofa synchronization signal which is also received at a track pulsegenerator which generates said track pulses.
 13. The method recited inclaim 11, wherein said serializing and modulating into multiplefrequency analog signals is performed by multiple modulator circuits,each modulator circuit operating at a different modulation frequency.14. The method recited in claim 13, wherein each said modulator circuitcontains digital-to-analog converters (DACs) coupled to modulatingmixers.
 15. The method recited in claim 11, wherein said modulating anddemodulating is performed in response to a quadrature amplitudemodulation (QAM) technique.
 16. The method recited in claim 15, whereinsaid quadrature amplitude modulation (QAM) encodes two analog messagesignals into carrier waves at each output frequency.
 17. The methodrecited in claim 15, wherein said quadrature amplitude modulation (QAM)is selected from the group of QAM orders consisting of QAM8, QAM16,QAM32, QAM64, QAM128 or QAM256.
 18. The method recited in claim 11,wherein said de-serializing and demodulating from multiple frequencyanalog signals is performed by multiple demodulator circuits, eachdemodulator circuit operating at a different modulation frequency. 19.The method recited in claim 18, wherein each said demodulator circuitcontains analog-to-digital converters (ADCs) coupled to demodulatingmixers.
 20. The method recited in claim 11, wherein said synchronizationsignals timed in relation to restoration of the track pulse, comprises:a first synchronization signal which triggers demodulator output ofdigital data to data buffers; a second synchronization signal whichlatches said digital data onto the data buffers; and a thirdsynchronization signal which indicates that the latched digital data canbe read from the buffers.